Senior Verification Specialist
5 days ago
Job Summary
Saxon Global is seeking a highly skilled Senior Verification Specialist to join our team. As a key member of our digital verification team, you will be responsible for designing and implementing verification environments for ASICs and FPGAs using SystemVerilog and UVM.
Key Responsibilities
- Design and implement VHDL test benches for the verification of ASICs and FPGAs
- Apply the Universal Verification Methodology (UVM) to develop verification environments
- Contribute to the development of test infrastructure and document problems found to designers
- Support laboratory testing and provide technical guidance to junior team members
Requirements
- Experience in writing test benches in SystemVerilog
- Knowledge of VHDL sufficient to navigate through an existing design
- Knowledge of UVM validation environments and Mentor Graphics' QuestaSim digital simulator
- Knowledge of the Linux environment, scripting languages (Shell, Tcl, Python, makefile), and testbed automation techniques (Jenkins)
- Knowledge of source code management techniques (SVN, GIT)
- Bachelor's degree in electrical engineering, computer engineering, or equivalent
- 10+ years of experience in digital verification
- Good interpersonal communication and teamwork skills
- Good oral and written communication skills in French and English
- Familiarity with Agile and Jira development methods
- Multitasking ability
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