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Test Access Mechanisms Engineer

2 months ago

Mountain View, California, United States Acceler8 Talent Full time

DFT Engineer

Acceler8 Talent is seeking a skilled DFT Engineer to contribute to innovative solutions in the realm of silicon and distributed systems. This organization is at the forefront of developing technologies that enhance the efficiency of computing workloads, significantly impacting global data center operations.

As a pivotal member of the engineering team, you will be instrumental in advancing the performance and scalability of distributed computing architectures. We welcome talented individuals with a strong background in large-scale networking and computing chips to explore this exciting opportunity.

Job Overview: DFT Engineer

Key Responsibilities

  • Collaborate with interdisciplinary teams to execute state-of-the-art designs in test access mechanisms, including IO BIST, memory BIST, and scan compression.
  • Engage with third-party IP vendors to seamlessly integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a sophisticated streaming scan fabric with a sequential scan compressor/decompressor.
  • Work closely with DFT Solutions Vendors to adapt patterns at the top level, implement the Memory BIST interface in high-performance processor IP, and facilitate high-speed I/O for logic scan tests.
  • Coordinate with Physical Designers to ensure DFT timing constraints are validated effectively.
  • Collaborate with RTL Designers to verify adherence to test design rules.
  • Partner with Test Engineers to establish patterns on Automated Test Equipment (ATE).
  • Contribute to the formulation and execution of DFT methodologies for next-generation products.

Qualifications

  • Master's degree in Electrical Engineering or equivalent experience.
  • Over 7 years of experience in DFT or related fields.
  • Extensive knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
  • Strong analytical capabilities in the verification and validation of test patterns and logic on complex, multi-million gate designs using vendor tools.
  • Familiarity with cross-functional areas such as RTL and clock design, STA, place-and-route, and power to ensure optimal trade-offs.
  • Experience in silicon debug and bring-up on ATE, with a solid understanding of pattern formats, failure processing, and test program development.
  • Proficient programming and scripting skills in Perl, Python, or Tcl are preferred.
  • Excellent written, verbal, and interpersonal communication skills, coupled with a strong desire to tackle unique challenges.