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Verification Engineer

2 months ago

Austin, Texas, United States Bayone Full time
About the Role

We are seeking a highly skilled Verification Engineer to join our System IP team at Bayone. As a key member of our team, you will be responsible for contributing to the functional verification of complex System IP designs, including coherent interconnect and LLC design.

Key Responsibilities
  • Develop and execute functional verification strategies for complex System IP designs
  • Design and implement feature-based test plans
  • Collaborate with the DV team and designers to build verification environments
  • Develop UVM sequences, tests, scoreboards, monitors, and checkers
  • Write SVA assertions and achieve functional and code coverage closure
  • Perform regression triaging and debug
  • Work on multiple tasks and projects with agility
Requirements
  • BS/MS/PhD in Computer Science or related field (or equivalent experience)
  • 12+ years of relevant experience in Verification
  • Expertise in System Verilog and UVM
  • Deep understanding of constrained randomization and efficient test suite development
  • Proficiency in script languages like Perl or Python
  • Working knowledge of C++
  • Good knowledge of memory subsystems, including interconnect and last-level cache
  • Familiarity with Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols
  • Excellent communication skills and ability to work as a team player