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Advanced ASIC FPGA Verification Engineer

4 weeks ago

Scottsdale, Arizona, United States General Dynamics Corporation Full time
Job Description

As a highly skilled ASIC FPGA Verification Engineer, you will play a critical role in the development of advanced defense platforms. You will be responsible for defining, designing, verifying, and documenting ASIC and/or FPGA developments, determining architecture, system simulation, and detailed design approach, and creating test and simulation plans that establish functional criteria.

Key Responsibilities:

  • Define module interfaces and all aspects of device design and simulation
  • Create test and simulation plans that establish functional criteria
  • Verify test results and analyze performance
  • Review vendor capabilities and simulation tools
  • Participate in the improvement of the ASIC/FPGA organizational processes
  • Support the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
  • May provide leadership and/or direction to lower-level employees

Requirements:

  • Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering, or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience
  • Department of Defense TS/SCI security clearance is preferred at time of hire
  • Candidates must be able to obtain a TS/SCI clearance within a reasonable time from date of hire
  • U.S. citizenship is required

Preferred Skills:

  • 3+ years experience verifying FPGAs or ASICS
  • In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
  • In-depth knowledge of System Verilog object-oriented programming and the Universal Verification Methodology (UVM)
  • Understanding of UVM Testbench Architectures
  • Comfortable using and developing UVM agents, bus functional models
  • Understanding of different types of coverage, usage of cover classes, cover points, etc.
  • Experience with predictive testbench components, functional coverage, and assertions
  • Experience with constrained random testing
  • Experience with the Register Abstraction Layer
  • Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies, etc.
  • Experience with scripting languages such as Linux shell scripts, TCL, Python
  • Familiarity with using Formal Verification tools, code coverage, writing waivers, etc.
  • Familiarity with the following are also helpful: Questa Verification IP (QVIP), developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs, AXI protocols, PCIe, Space Wire, and Ethernet interfaces, DSP functions and common signal processing components, familiarity with debugging FPGA/ASIC hardware and assisting with HW/SW integration, Continuous Integration features of GITLab

What We Offer:

  • An exciting career path with opportunities for continuous learning and development
  • Research-oriented work, alongside award-winning teams developing practical solutions for our nation's security
  • Flexible schedules with every other Friday off work, if desired (9/80 schedule)
  • Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more

Workplace Options:

This position is fully on-site or hybrid/flex, as mutually agreed. While on-site, you will be a part of the Scottsdale, AZ team.

Keywords: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing