CPU Block-Level Design Specialist

6 days ago


Beaverton, Oregon, United States Apple Full time
Synopsis

We are seeking a highly skilled CPU Physical Design Engineer to join our team in Beaverton, Oregon. In this role, you will be responsible for driving RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals.

You will work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design.

  • Main Responsibilities:
  • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals
  • Responsible for block-level physical design delivery along with closure of backend flows, electrical requirements, and improving silicon yield
  • Work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design
  • Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability
  • Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA


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