Design Verification Engineer
4 weeks ago
We are seeking a highly skilled Design Verification Engineer to join our dynamic team at Apple. As a key member of our group, you will play a critical role in shaping the development of our cutting-edge products.
Key Responsibilities- Develop and implement comprehensive verification plans for SoC/IP designs, ensuring bug-free first silicon.
- Design and develop verification environments, including stimulus, checkers, assertions, and trackers.
- Collaborate with cross-functional teams to ensure seamless integration and delivery of high-quality products.
- Develop and maintain detailed test and coverage plans, ensuring scalability and portability.
- Track and report verification progress, utilizing metrics such as bugs and coverage.
- Deep knowledge of SystemVerilog test-bench language and UVM.
- Experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
- Experience with serial protocols such as PCIe or USB.
- Experience with mixed-signal verification methodology for IPs such as PHYs, PLLs, etc.
- Deep knowledge of one of the scripting languages: Python, Perl, TCL.
- Deep knowledge of formal verification methodology.
BS degree in a technical discipline with a minimum of 10 years of relevant experience.
Additional RequirementsApple is an equal opportunity employer committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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