Wireless SOC Design Verification Engineer
2 weeks ago
As a Design Verification Engineer on our team, you will play a critical role in crafting and productizing state-of-the-art Wireless SoCs. This position requires someone comfortable with all areas of SOC design verification engineering.
Key Responsibilities- Create coverage-driven verification plans from specifications, review, and refine to achieve coverage targets.
- Architect UVM-based highly reusable test benches and integrate complex multi-instance VIPs, subsystem test benches, and test suites to SOC level.
- Achieve targeted coverage, work with design, architecture, SW, FW, and external IP delivery teams to efficiently integrate and verify overall SOC design.
- Work closely with DV methodology architects to improve verification flow.
We are looking for a dedicated and hands-on ASIC DV engineer with advanced knowledge of HVL methodology (UVM/OVM) and experience in UVM. Some experience with formal verification is a plus. Proven track record of working full ASIC cycle from concept to tape-out to bring-up is required. Experience taping out large SOC systems with embedded processor cores and hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment is necessary.
What We OfferAt Apple, we offer a comprehensive compensation package, including base pay, discretionary bonuses, and commission payments. You will also receive benefits such as comprehensive medical and dental coverage, retirement benefits, a range of discounted products, and free services. Additionally, you will be eligible for discretionary restricted stock unit awards and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan.
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