Digital Design Engineer

3 weeks ago


San Francisco, California, United States Capgemini Full time
Job Description

Capgemini is seeking a highly skilled RTL Design Engineer to join our team. As an RTL Design Engineer, you will be responsible for designing and developing ASICs for various applications, including Memory Controllers, Video, AR, VR, and MR.

Key Responsibilities:

  • Develop micro architectural documents from requirements specifications.
  • Design and develop RTL code using Verilog and SystemVerilog.
  • Perform basic linting and quality checking.
  • Collaborate with the SoC integration team as needed.

Requirements:

  • Minimum 10 years of experience in digital design at the RTL level using Verilog and SystemVerilog.
  • Experience in developing micro architectural documents from requirements specifications.
  • Conceptual design experience, with a focus on ASIC design.
  • Experience in applying linting and quality checking techniques.
  • Strong knowledge of SystemVerilog and EDA tools such as Cadence and Synopsys.
  • Excellent communication and collaboration skills.
  • Experience in designing for Video, AR, VR, or MR applications.

Preferred Qualifications:

  • Experience with DMA, memory controller, and MIPI protocols.
  • Knowledge of DSI/CSI, data and control path pipeline design, interconnect, and AMBA interfaces.
  • Experience with RTL design automation using Python scripting.

About Capgemini Engineering

Capgemini Engineering is a world leader in engineering and R&D services, combining industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds. We help clients accelerate their journey towards Intelligent Industry.

Why Join Us?

At Capgemini, we offer a range of benefits to support your well-being, including flexible work arrangements, healthcare, financial well-being programs, and paid time off. We also offer opportunities for professional growth and development, as well as a collaborative and inclusive work environment.



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