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High-Performance Cache Design Engineer
2 months ago
**About the Role**
We are seeking an experienced CPU Cache Architect to join our team at Apple. As a key member of our Silicon Engineering Group, you will be responsible for driving the development of high-performance, low-power microprocessors that power our innovative products.
**Key Responsibilities**
- Develop and specify micro-architecture designs for CPU multi-level cache subsystems
- Own or participate in the development of RTL design, assessment, and refinement to target power, performance, area, and timing goals
- Support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
- Explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
- Work with multi-functional engineering teams to implement and verify physical design on aspects of timing, area, reliability, testability, and power
**Requirements**
- Minimum BS and 10+ years of relevant industry experience
- Thorough knowledge of microprocessor architecture, including expertise in one or more of the following areas:
- Coherence protocols and interconnects
- High-performance design techniques
- Memory subsystem queuing, scheduling; starvation and deadlock avoidance
- SRAM design basics
- Multiple clock/power domains and power management strategies
- Prefetchers, replacement policies
- Debug capabilities
- DFT strategies
- Error detection and correction
- Knowledge of Verilog and/or VHDL, experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
- Understanding of low-power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C++ programming
- Experience using an interpretive language such as Perl or Python
**Preferred Qualifications**
- Minimum BS and 10+ years of relevant industry experience