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Design Verification Engineer
2 months ago
We are seeking a highly skilled Design Verification Engineer to join our team at Apple. As a key member of our silicon design group, you will be responsible for verifying high-throughput, complex cellular baseband modems and transceiver link controllers.
Key Responsibilities- Design and productize state-of-the-art cellular baseband modems and RF link controllers targeted for SOCs.
- Verify high-quality complex IPs and Sub-System designs by working closely with cross-functional teams.
- Develop reusable verification environments to achieve quality goals.
- Collaborate with other product development groups across Apple to push the industry boundaries of what cellular systems can do.
- Work closely with DV methodology architects to improve verification flow.
- Execute test plans from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions, report verification progress against test plan and coverage metrics.
- BS and 3+ years of relevant industry experience.
- Strong knowledge of System Verilog and UVM.
- Good understanding of System C, C/C++, Python/perl.
- Experience in developing and establishing DV Methodologies.
- Ability to develop System Verilog Testbench with UVM methodology from scratch.
- Experience in C/C++ modeling for design verification is a plus.
- Experience with constraint random testing, SVA, Coverage driven verification.
- Good test planning and problem-solving skills.
- Knowledge of 4G/5G cellular physical layer operation (3GPP) is a plus.
- Experience with verification of embedded processor cores.
- Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
- Comprehensive medical and dental coverage.
- Retirement benefits.
- A range of discounted products and free services.
- Reimbursement for certain educational expenses.
- Discretionary bonuses or commission payments.
- Relocation assistance.