Senior RFIC Layout Engineer
2 days ago
We are seeking a highly skilled Senior RFIC Layout Engineer to join our team at Kyocera International, Inc. in San Diego, California.
Job Summary:The successful candidate will be responsible for providing technical guidance, mentorship, and leadership to a team of layout engineers. They will also be responsible for performing detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, phase shifters, bias, and power management and integration digital IPs.
Responsibilities:- Provide technical guidance, mentorship, and leadership to a team of layout engineers.
- Perform detailed transistor-level layout of RF and analog circuit blocks.
- Take ownership of the chip's top-level integration, ensuring seamless integration of various RF and analog blocks, meeting performance and power targets, and resolving any layout-related challenges.
- Lead and coordinate the tapeout process, collaborating with cross-functional teams, such as design, verification, packaging, manufacturing and foundry to ensure a successful and timely tapeout of the chip.
- Demonstrate a deep understanding of advanced RFIC layout techniques and methodologies.
- Drive the development of best practices for efficient and reliable layout design.
- Oversee the DRC, LVS and DFM checks to ensure compliance with design specifications and foundry rules.
- Work closely with design engineers to resolve any layout-related issues.
- Collaborate with process technology and foundry partners to understand the latest technology nodes and design requirements, ensuring designs are optimized for manufacturability.
- Conduct thorough layout reviews, providing constructive feedback to the team.
- Take responsibility for layout sign-off before tapeout, ensuring the highest quality standards are met.
- Stay updated on the latest layout design methodologies, tools, and industry trends.
- Identify opportunities for process improvement and efficiency gains in the layout design flow.
- Create checklists to insure best practices.
- Oversee block level and top-level layout through the full verification flow, including extraction, DRC, LVS, and DFM checking.
- Collaborate with designers on placement, block level, and top-level floorplanning.
- Conduct layout reviews for power/ground routing, electromigration, signal path check, matching, and signal coupling.
- Manage top-level layout integration and verification, ensuring adherence to schedules.
- Bachelor's degree in Electrical Engineering or related field, with at least 10+ years of relevant industry experience.
- Extensive industry experience in custom RF/analog layout for RF transceivers with a strong knowledge of deep sub-micron CMOS and SOI processes.
- Demonstrated ability to lead and mentor a team of layout engineers effectively.
- Strong communication and interpersonal skills to collaborate with cross-functional teams.
- Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Mentor Calibre,...) and familiarity with layout design flows for advanced technology nodes.
- Strong analytical and problem-solving skills to identify and address layout-related issues efficiently.
- Proficient in layout techniques for device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.
- Meticulous attention to details, ensuring the highest level of accuracy and quality in all layout designs.
- Familiarity with semiconductor manufacturing processes and foundry technologies.
- Ability to thrive in a fast-paced, dynamic work environment and adapt quickly to changing project requirements.
- Solid understanding of RC delay, electromigration, and coupling effects.
- Familiarity with guard rings, DNW, PN junctions, NTN/BFMOAT and advanced process effects such as LOD, WPE.
- High level of proficiency in interpreting DRC, ERC and LVS.
- Excellent communication skills with the ability to collaborate effectively with cross-functional teams.
- Capability to lead other layout engineers for top-level integration.
- Ability to identify failure-prone circuit and layout structures and proactively work with circuit designers to resolve problems.
- Scripting skills in PERL or SKILL are a plus, but not required.
$170,000 - $275,000
Additional Information:The above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required.
The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time.
This position may require exposure to information subject to US export control regulations, i.e. the International Traffic in Arms Regulation (ITAR) or the Export Administration Regulations (EAR).
Kyocera International, Inc. values diversity in its workforce, and is proud to be an AAP/EEO employer.
All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.
If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Kyocera International, Inc.'s Human Resources team directly.
Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.
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