Senior SOC Physical Design Engineer

6 days ago

Washington DC USA, United States Synopsys Full time
SOC Physical Design Engineer Opportunity

At Synopsys, we are driving the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

About the Role
As a SOC Physical Design Engineer, you will be a seasoned professional with a deep understanding of the full SOC design cycle, particularly focusing on physical design. You will be proficient in Synopsys tools, have a strong track record of delivering high-quality tape-outs, and excel in a collaborative environment, working well with cross-functional teams to meet SOC development objectives. Your experience spans various technology nodes, and you are adept at managing complex IP sub-systems. You will bring a proactive approach, recognizing and mitigating risks while ensuring high standards of quality.

Key Responsibilities
  • Implementing SOC physical design from RTL to GDSII.
  • Working on SOC top-level and block-level physical design implementation and design closure.
  • Developing and improving methodologies and flows within Synopsys and customer environments.
  • Collaborating with customer teams, acting as an extension of their design team.
  • Managing top-level floor-planning, bump-maps, RDL IO Pad/Ring creation/verification, and power grid creation/verification.
  • Defining sign-off requirements and margins based on Foundry technology requirements.

Impact and What You'll Be Doing
You will contribute to the successful implementation and design closure of SOC projects, enhance Synopsys' reputation for delivering high-quality silicon solutions, drive innovation in SOC physical design methodologies and flows, and ensure first-time right silicon through meticulous design and verification processes.

Requirements
  • BS or MS with 8+ years of experience in SOC physical design.
  • Proficiency with Synopsys tools such as DC, DCG, DC TOPO, Fusion Compiler/ICC2, and Lynx.
  • Experience with top-level floor-planning, clocking methodologies, and power grid creation/verification.
  • Understanding of DFT structures, formal verification, and UPF flows.
  • Experience with GlobalFoundries, TSMC, and Samsung technology nodes.

Why You'll Thrive Here
You will be a collaborative team player who works well in cross-functional environments, a proactive problem solver with a keen eye for detail, adaptable and able to manage risks and contingency plans effectively, passionate about innovation and continuous improvement, and capable of working independently and driving projects to successful completion.

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