Senior Staff Engineer, SOC Design Verification

4 weeks ago


San Diego, California, United States GreenWave Radios Full time
Design Verification Engineer

GreenWave Radios is seeking a highly skilled Design Verification Engineer to join our team in San Diego, Irvine, or San Jose, California. As a key member of our ORAN SoC product design verification team, you will lead and contribute to the development and execution of design verification plans.

Key Responsibilities:
  • Develop a testbench environment to verify the design at the IP/ Subsystem and SoC Levels using SystemVerilog and UVM.
  • Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level.
  • Develop and execute verification plans based on design specifications and collaboration with architects and designers.
  • Construct HW/SW Co-Verification environment - test-benches, use-cases, APIs, sequences.
  • Execute and Debug use-cases.
  • Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modeling (TLM), HW emulation/acceleration, and SW-driven verification.
  • Debug test cases and report verification results to achieve expected code/functional coverage metrics.
  • Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.
  • Assist in emulation, FPGA, and prototyping efforts.
  • Implement and maintain automated verification flows in Python and Perl/ Shell scripts.
Requirements:
  • Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.
  • 15 or more years of experience in design verification with proven experience in full chip verification from test plan development to tape-out sign-off.
  • Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).
  • Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from the scratch.
  • Experiences in multi-core ARM processors and bus-systems verification with VIP.
  • Experiences in PCIE G4/5/6 controller verification with Cadence VIP.
  • Proficient in System Verilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
  • Experience in developing IP/ Subsystem/ chip-level System Verilog and UVM based test bench environments, writing System Verilog Assertions (SVAs), with embedded software design and testing.
  • Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB etc.).
  • Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus.
  • Track record of successfully executing block or chip-level verification plans.
  • Excellent communication and presentation skills, energetic and self-motivated.
  • Work effectively with off-site/ offshore design and verification teams across locations.


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