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Digital Circuit Designer

2 months ago

Santa Clara, California, United States Ambarella Full time
Job Overview

At Ambarella, we're pushing the boundaries of innovation in computer vision and machine learning. We're seeking a highly skilled ASIC Design Engineer Intern to join our team and contribute to the development of cutting-edge video compression and image processing technologies.

Responsibilities:

* Design and implement video compression logic, image processing logic, vector processing, and neural network accelerator logics, and processor cores in Verilog and System Verilog.
* Develop and optimize RTL for timing, area, and power using advanced design tools and methodologies.
* Create unit-level and cluster-level test benches, BFM, random test generators, functional coverage monitors using System Verilog, UVM, C++, and Perl scripts.
* Develop test plans, random and directed test cases, perform logic verification, and functional coverage analysis.
* Collaborate with cross-functional teams to develop front-end methodologies and tool flows.
* Participate in chip bring-up and testing.

Requirements:

* Master's degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.
* Strong understanding of computer architecture, logic design, and VLSI design.
* Proficiency in System Verilog, Verilog, and Perl.
* Knowledge of design verification and functional coverage.
* Ability to program scripting languages and write assembly language programs.
* Excellent communication skills and a strong team player.
* Knowledge of logic synthesis and timing closure is a plus.

If you're passionate about designing innovative digital circuits and contributing to the development of cutting-edge technologies, we encourage you to apply for this exciting opportunity.