Senior GPGPU Design Engineer

2 months ago

San Francisco, California, United States Sql Pager LLC Full time
About the Role

We are seeking a highly skilled Senior GPGPU Design Engineer to join our team at Sql Pager LLC. As a key member of our engineering team, you will be responsible for designing and developing high-performance GPGPU architectures for our artificial intelligence computing platform.

Key Responsibilities
  • Participate in the definition and modeling of GPGPU architectures, including verification test plans and testbench architectures.
  • Develop micro-architecture specifications, RTL in Verilog/System Verilog, and performance/speed/power goals.
  • Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoCs.
  • Define micro-architectures for the implementation and usage of functional block IPs, possibly with external sourced IPs.
  • Participate in SoC level integration and verifications.
  • Work with the Physical design team for timing closure.
Requirements
  • 10+ years of experience as a GPGPU Digital Design Engineer (Principal), 7+ years (Senior Staff), or 5+ years (Staff).
  • Experience in converting module-level micro-architecture definitions from given marketing requirements.
  • Expertise in RTL Logic Design, CDC, RDC, Scan insertion, Lint, LEC, and synthesis with timing constraints.
  • Experience in low-power design with UPF.
  • Scripting experience with Tcl, Python (or similar) language.
  • At least gone through entire ASIC design phases, from micro-architecture to post-silicon bringing-up, and validation.
  • In-depth knowledge of one of the parallel processing hardware architectures, such as Neural Network Computation Flow on GPU/NPU, Array/Vector/Systolic Processors, SIMD/SIMT Processing Pipelines, Base Jump manycore, GPU cache hierarch, and Latency-hiding with NoC Inter-connect bus fabric.
Preferred Qualifications
  • Prior experience of GPU functional blocks, including Caches.
  • Knowledge in various DNN networks and their core ASIC implementations.
  • Knowledge of Graphics/Compute APIs, such as CUDA/OpenCL.
  • Knowledge of OS, software/hardware interface.
  • Finite Precision Analysis of multi-layer compute processing pipeline.
Education

BSEE/BSCE or equivalent. Master's degree in science is preferred, but not required.

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