Cache Coherency Architect

NextDeavor is seeking a highly skilled Cache Coherency Architect to join our team. As a key player in our advanced IP portfolio, you will be responsible for defining and optimizing cache coherency solutions that drive innovation and efficiency in our NoC IP offerings.

• Cache Coherency Architecture: Evaluate existing protocols, maintain and improve our proprietary coherency protocol, and develop comprehensive architectures that align with SoC design.
• NoC Integration: Collaborate with SoC design teams to ensure seamless integration of cache coherency into the SoC architecture and optimize Cache Coherency Architecture and uArchitecture within the NoC.
• Performance and Power Optimization: Analyze performance bottlenecks and power consumption aspects, proposing and implementing innovative solutions to enhance overall efficiency.
• Protocol Verification: Support the verification team to develop verification strategies to ensure the correctness and robustness of cache coherency protocols and the implementation within our NoC IP.
• Cross-Functional Collaboration: Interact with marketing and sales teams to collect customer input, collaborate with hardware design, software development, and system architecture teams, and provide technical expertise to the FAE team.
• Industry Research and Innovation: Stay up-to-date with the latest advancements and research in cache coherency and NoC technologies, evaluating emerging methodologies, standards, and industry trends to enhance our NoC IP offerings.
• Documentation and Communication: Prepare detailed technical documentation and effectively communicate complex technical concepts to both technical and non-technical stakeholders.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Proven experience as a Cache Coherency Architect, Design Engineer, or similar role with a focus on NoC IP development.
• In-depth knowledge of SoC and NoC architecture, cache coherency protocols, and memory hierarchy.
• Strong understanding of cache hierarchies and their interaction with NoC interconnects.
• Experience in cache coherency verification and validation techniques.
• Familiarity with hardware description languages (HDLs) and SoC design tools.
• Strong analytical and problem-solving skills with a strategic mindset.
• Excellent communication and collaboration abilities to work effectively with diverse teams and stakeholders.

Pay Range: $175,000 to $235,000 annually