Senior Physical Synthesis Implementation Engineer
4 weeks ago
As a Senior Physical Synthesis Implementation Engineer at Qualcomm, you will play a crucial role in defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development for high-performance, high-quality, low-power world-class products.
Key Responsibilities- Implement hierarchical blocks of the DDR/system cache subsystem using Synopsys Fusion Compiler for physical synthesis.
- Collaborate with RTL designers to manage complex power intent and troubleshoot UPF issues in synthesis.
- Manage timing constraints and run Conformal Low Power Checks on final netlists to resolve CLP violations.
- Run Power Aware Conformal Logic Equivalency Checks on both RTL and Gate levels.
- Support PD timing/congestion closure and work with RTL designers and PD teams to evaluate and execute manual and tool-generated functional checks.
- Bachelor's degree in Engineering and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Engineering and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Engineering and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Bachelor's or Master's degree in Engineering.
- 8+ years of Hardware Engineering experience or related work experience.
Qualcomm offers a competitive annual discretionary bonus program and opportunity for annual RSU grants. Our highly competitive benefits package is designed to support your success at work, at home, and at play.
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