Senior CAD Engineer

3 weeks ago


San Diego, California, United States Apple Full time
About the Role

We are seeking a highly skilled CAD Engineer to join our team at Apple. As a CAD Engineer, you will be responsible for designing and developing physical design verification (PDV) flows for our next-generation, high-performance, power-efficient processor, system-on-chip (SoC).

You will work closely with our custom digital/analog/mixed-signal design, physical design (PD), and chip integration teams to ensure seamless and efficient handling of tasks that make our products beloved by millions.

Key Responsibilities
  • Develop, improve, and maintain various aspects of physical verification flow and methodology
  • Coordinate the effort of validating flows, improving for custom checks and data generation
  • Work with the design and PD teams to facilitate the chip design process
  • Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
  • Collaborate with tool vendors and foundries for PDK performance enhancements
Requirements
  • Previous industry experience in Silicon chip design flows
  • Tapeout support and IP/SOC level PDV debug experience in various technology nodes
  • Scripting skills in programming languages such as Python, Perl, Tcl, Shell, Makefile, or C
  • Experience with flow automation and development in advanced nodes
  • Minimum requirement of BS and 10+ years of relevant industry experience
Preferred Qualifications
  • Knowledge in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL
  • Rule coding in PERC is a plus
  • Knowledge of parasitic extraction, SKILL coding, and PnR tools is a plus

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