Principal Package Design Engineer
2 weeks ago
This Series B AI semiconductor startup is revolutionizing the industry with cutting-edge hardware, software, and systems that tackle the critical bottlenecks in next-gen computing workloads – at any scale – across hyperscale cloud, edge, enterprise, 5G/6G, and automotive infrastructure. With $125 million in funding, they're poised to grow their world-class team.
As a Principal Package Design Engineer, you'll take ownership of large-scale, challenging designs from concept through production, contributing across the entire lifecycle of complex package and system development.
This is a full-time hybrid role in the San Francisco Bay Area.
Key Responsibilities
- Collaborate with cross-functional teams on package planning and integration.
- Develop package specifications and perform analysis for high-speed serdes interfaces.
- Conduct bring-up, testing, and characterization of high-speed serdes and memory interfaces.
- Analyze HBM and other advanced packaging technologies.
- Specify and analyze power and high-speed signaling requirements for high-speed networking systems.
- Work with systems engineers to define and implement thermal management solutions.
- Support operations team during package qualification and failure analysis processes.
Requirements
- Minimum qualification of MS or PhD in Electrical Engineering or Mechanical Engineering, with over 10 years of relevant experience.
- Proficient in hands-on design of large body size, high power, high speed substrates using Cadence APD/SIP.
- Strong expertise in Signal Integrity and Power Integrity, with mastery of Ansys HFSS and SiWave.
- Familiarity with package and PCB materials and their properties.
- Experience with 2.5D packaging and interposer integration is advantageous.
- Demonstrated success in leading substrate layout engineering teams.
- Direct involvement in production qualification and post-production activities.
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