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Expert Analog Layout Engineer
2 months ago
Senior CMOS ASIC Layout Engineer
We are seeking a highly skilled CMOS Layout Engineer to contribute to a custom chip design project. This role requires extensive experience in layout, particularly with TSMC processes.
Responsibilities:
- Proficient in custom analog layout, including floorplan, placement, routing, and verification.
- Ability to assess trade-offs related to matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up.
- Strong command of Cadence Virtuoso and Mentor Calibre, with the capability to interpret verification results for DRC, LVS, ERC, and ANT.
- Collaborate proactively with circuit designers to devise optimal solutions and identify potential failure-prone circuit and layout structures.
- Deliver precise scheduling and updates to align with project milestones.
Qualifications:
- Experience in analog mixed signal/CMOS layout.
- Familiarity with TSMC processes.
- Expertise in the 40-90 nm range.
- Knowledge of SMC high voltage nodes.
- Proficient in Cadence Virtuoso (layout and LVS).
- Experience with Voltus (Simulation).
- Skilled in Calibre (DRC).
Compensation:
Estimated Minimum Rate: $52.50
Estimated Maximum Rate: $75.00
Note:
The displayed pay ranges are estimations. Actual compensation is based on the applicant's experience, technical skills, and other qualifications outlined in the job description. All qualified candidates are encouraged to apply.
Yoh, a Day & Zimmermann company, is committed to equal opportunity employment.
All qualified applicants will be considered for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
For individuals with disabilities requiring accommodation in the application process, please reach out to us.
