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DRAM Engineer
2 months ago
Etched is seeking a skilled DRAM Engineer to advance our memory systems. As a DRAM Engineer at Etched, you will collaborate with design and verification teams to optimize memory controllers and PHYs, perform DRAM simulations, validate SoC memory integration, and oversee HBM silicon and package testing.
Key Responsibilities:- Collaborate with design, verification, and integration engineers to define memory controller and PHY requirements.
- Work with Memory Controller, DDRPHY/HBMPHY, and DRAM vendors to optimize main memory performance and power.
- Perform DRAM simulations to ensure they meet Etched's requirements.
- Validate SoC memory controller and PHY integration and help verification of features in simulation and emulation.
- Oversee internal and external HBM silicon and package level testing.
- Develop bring-up and debug methodologies for DDR and HBM interfaces.
- Perform Post-Si validation.
- Minimum 5 years of experience.
- Knowledge of DRAM architectures and memory organization.
- Experience with DRAM simulation and interface verification (HBM2E/HBM3 PHY, Memory Controller).
- Understanding of memory test patterns and DRAM reliability.
- Excellent hardware and software debugging skills.
- Strong teamwork and interpersonal skills.
- Understanding of computer architecture and micro-architecture.
- Programming experience in C/C++/Python.
- Preferred: Master's or PhD Degree with 3 years of relevant industry experience. Experience with HBM2E/3/3E/DDR5/LPDDR4+ based products.
- Minimum: Bachelor's degree with a minimum of 5 years relevant industry experience. Experience with HBM2E/3/3E/DDR5/LPDDR4+ based products.
- Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents.
- Housing subsidy of $2,000/month for those living within walking distance of the office.
- Daily lunch and dinner in our office.
- Relocation support for those moving to Cupertino.
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
Our Culture:We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
