Senior DDR IP Design Engineer
4 weeks ago
At SpaceX, we're pushing the boundaries of innovation and technology. As a Senior DDR IP Design Engineer, you'll play a critical role in developing cutting-edge memory controller IP for our next-generation SoCs. With a strong background in VLSI design and a passion for delivering high-quality solutions, you'll collaborate with cross-functional teams to design, develop, and integrate memory controller and PHY IP cores.
Responsibilities:
- Own the high-quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects and addressing issues.
- Responsible for Memory Controller/PHY IP core development and integration.
- Collaborate with chip architects, software engineers, and other subsystem owners to develop high-performance Memory controller/PHY solutions.
- Write detailed design specifications and test plans in close collaboration with architecture, package, and verification engineers.
- Support silicon bring-up, performance, and power characterization for memory subsystems.
- Drive functional verification, including test plan reviews, and functional and code coverage as well as timing closure for your designs.
Requirements:
- BS in Electrical Engineering, Computer Engineering, or Computer Science.
- 8+ years of experience working with ASICs and the VLSI design flow.
- Experience in RTL development and verification using Verilog and/or SystemVerilog.
Preferred Skills:
- MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Knowledge of DDR/LPDDR DRAM protocols and experience analyzing/debugging DDR interfaces and protocols.
- Experience in the development of Memory Controller and PHY IPs.
- Experience working with Memory IP, Error checking Code (ECC), and building scalable, efficient flows and processes.
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