Deep Learning Compiler Engineer for Ryzen AI NPU
4 weeks ago
We are committed to enriching our industry, communities, and the world through innovative AMD technology. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded. At AMD, we push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
The RoleWe are seeking a talented Machine Learning (ML) Compiler SW Engineer to join our growing team in the AI group and play a crucial role in developing SW toolset to deploy cutting-edge ML models on AMD's XDNA Neural Processing Units (NPU). You will be responsible for designing, implementing, and optimizing compilers that translate Gen-AI ML inference models like SDXL-Turbo, Llama2, Mistral, etc. into low-level code for specialized hardware architectures. Your work will directly impact the efficiency, scalability, and reliability of our ML applications.
Responsibilities- Design and develop novel algorithms for tiling and mapping quantized ML workloads on Ryzen AI NPU.
- Analyze and transform intermediate representations of ML models (computational graphs) for efficient execution.
- Collaborate with architects and runtime software engineers to understand performance requirements of different operators and translate them into effective compiler strategies.
- Collaborate with kernel developers to understand kernel tiling requirements and strategize the dataflow and L1/L2 buffer allocation schemes.
- Develop back-end optimization passes to convert high-level representation into driver calls.
- Implement compiler optimizations for performance, resource usage, and compute efficiency.
- Develop and maintain unit tests and integration tests for the compiler to support different generations of NPU architecture.
- Enable detailed profiling and debugging tools for analyzing performance bottlenecks and deadlocks in dataflow schemes.
- Strong understanding of the dataflow scheduling and memory hierarchy in a multi-core processor architecture.
- Knowledge of compiler design principles (front-end, middle-end, back-end).
- Experience with machine learning frameworks (e.g., TensorFlow, PyTorch).
- Experience working with ML compilers (e.g., MLIR, TVM).
- Experience with ML models such as CNN, LSTM, LLMs, Diffusion is a must.
- Excellent programming skills in Python, C++, or similar languages.
- Experience with machine learning hardware architectures (e.g., GPUs, TPUs, VLIW) is a plus.
Master's degree or PhD. in Computer Science, Engineering, or a related field (or Bachelor's degree with significant experience).
LocationSan Jose, Ca
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