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Senior Physical Design Engineer for SoC Integration

2 months ago


Mountain View, California, United States Google Full time
About the Role

At Google, we're pushing the boundaries of technology to make computing faster, seamless, and more powerful. As a Senior Physical Design Engineer for SoC Integration, you'll play a critical role in developing and executing SoC integration flow development and execution.

Key Responsibilities
  • Develop, support, and execute SoC integration flow development and execution, including multiple scenarios of die size planning, bump planning, IO and block placements, power regions planning, layout routing planning, and product graphics grid with multiple power regions.
  • Be responsible for bump/micro-bump to package integration planning and implementation of package-driven feedback into high-level design.
  • Ensure SoC integration is block-friendly, easy to implement, and meets power, performance, and area goals.
  • Ensure multiple power domains electromigration/voltage (EM/IR) and bump planning meet reliability requirements.
  • Own and drive execution of high-level SoC and partner with foundry to resolve issues related to new technologies.
Requirements
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with SoC Integration focused on low power design.
  • Experience with new process technology-based SoC integration flow development and tape-out.
  • Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow automation and data visualization.
  • Experience with physical design flow development and design closure for multiple ASIC/SoCs.
Preferred Qualifications
  • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
  • Experience in System-on-a-Chip (SoC) integration, including 2.5D and 3-dimensional integrated circuit integration and sign-off.
  • Experience in extraction of ASIC design parameters, Quality of Results (QoR) metrics, and analyzing trends.
  • Experience in co-optimization to enable schedule-sensitive development with consideration of block complexity, power domains, clocking, congestion, etc.