Senior ASIC RTL Design Engineer for Machine Learning Accelerators

4 weeks ago


Madison, Wisconsin, United States Google Full time
Job Summary

We are seeking a highly skilled ASIC RTL Design Engineer to join our team in developing custom silicon solutions for machine learning acceleration in Google's data centers. As a key member of our team, you will be responsible for designing and implementing Application-Specific Integrated Circuit (ASIC) used to accelerate machine learning computation.

Responsibilities
  • Define micro-architecture specifications and take ownership of one or more modules and implement Register-Transfer Level (RTL).
  • Create simple test benches and debug complex logic simulation.
  • Converge functionality and Power, Performance and Area (PPA) of the design.
  • Work closely with software teams to ensure solutions.
  • Contribute to design methodology, libraries and code review.
Requirements
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 2 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips.
  • Experience in logic design, functional, and Power, Performance and Area (PPA) closure.
  • Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
About the Team

Our team is responsible for developing and maintaining Google's data centers and building the next generation of Google platforms. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them.



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