ASIC/FPGA Design: Senior Member of Engineering Staff

5 days ago

Camden, United States L3 Technologies Full time
Job Title: ASIC/FPGA Senior Member of Engineering Staff

Job Code: 12189

Job Location: Camden, NJ (relocation can be provided for those that qualify)

Schedule: 9/80 Regular with every other Friday off

Job Description:

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.

L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).

This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Essential Functions:
  • Responsible for deriving engineering specifications from system requirements and developing detailed architecture
  • Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
  • Generate test plans
  • Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
  • Silicon/FPGA bring up, characterization and production ramp/support/collateral
Qualifications:
  • BSEE, MSEE Preferred.
  • 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
  • Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
  • Proficient with CDC, RDC. Formal EDA.
  • Proficient in VHDL is a must
  • Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
  • Strong logic/board debug, and analytical skills.
  • Experience with project leadership and EVM
  • Excellent written, verbal, and presentation skills.
  • Active SECRET Clearance
Preferred Additional Skills:
  • A big plus if the candidate possesses "any" of the following:
    • Proficiency in C++ (OOP)
    • Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
    • Knowledge of PCIe, NVMe, USB protocols.
    • Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).

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