RTL Design Engineer

2 weeks ago

Chandler, United States ACL Digital Full time
General RTL and ASIC development
  • Detailed module design, performance analysis and detailed design specification creation
  • Participate in the RTL implementation, synthesis, formality check as well as ECOs
  • Support post-layout timing closure and verification
  • Improve Data & Command processing bandwidth, reduce latencies & increase reliability
  • Support porting the design into emulation platforms
  • Support pre-tapeout verification and post-tapeout validation/characterization of the system designed
  • Work closely with FPGA support software and FW engineers to resolve hardware issues and customer issues

Ethernet MAC and PCS Development
  • Integrate 3rd party Ethernet MACSec and IPSEC into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register maps
  • Develop Block Level Constraints and run synthesis
  • Perform Static Timing Analysis of the MACSec digital logic and review post-layout timing
  • Support Verification and Validation groups in testing of the IP blocks and other similar logic blocks
  • Integrate and simulate memory controller designs including
    • Integration into processor sub-systems as needed.
    • Integration into IP used in the FPGA fabric of the device
  • Ongoing customer support to ensure the IP cores are robust with performance that meets the customer performance and/or power goals
  • Support RTL design engineers with less experience for the functions shown above
JOB Requirements
  • Experience in SOC IP development for Ethernet, secure communication standards, and associated protocols
  • Strong Experience in RTL design, design verification, synthesis & formality
  • Strong Experience in Static Timing Analysis and Verilog simulation tools
  • Should be able to design complex state machines & data path logic
  • Ability to write detailed design specifications
  • Good analytical, oral, and written communication skills
  • Able to write clean, readable presentations
  • Self-motivated, proactive team player
  • Ability to work to schedule requirements
Education Required
  • Bachelors/Master's in electrical engineering, Computer Engineering or Computer Science.
Experience Required
  • Minimum of 10 years of proven silicon design experience in high-speed RTL design, Ethernet, and other related logic
Beneficial Experience
  • FPGA and ASIC System On Chip Design Experience
  • Lab Experience for System Level Validation

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