Sr. ASIC Design Engineer, DDR IP

4 weeks ago

Redmond, United States Space Exploration Technologies Corp. Full time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER, DDR IP (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation SOCs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network. RESPONSIBILITIES: Own the high quality release of the Memory Controller IP for SpaceX SoC designs, including triaging release/integration issues into IP defects and addressing issues Responsible for Memory Controller/PHY IP core development and integration Responsible for RTL design, synthesis, timing constraints, power estimation, and timing analysis using industry-leading CAD tools in the latest generation process technologies Collaborate with chip architects, software engineers, and other subsystem owners to develop high performance Memory controller/PHY solutions Write detailed design specifications and test plans in close collaboration with architecture, package and verification engineers Support silicon bring-up, performance, and power characterization for memory subsystems Drive functional verification including test plan reviews, and functional and code coverage as well as timing closure for your designs BASIC QUALIFICATIONS: BS in Electrical Engineering, Computer Engineering, or Computer Science 8+ years of experience working with ASICs and the VLSI design flow Experience in RTL development and verification using Verilog and/or SystemVerilog PREFERRED SKILLS AND EXPERIENCE: MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science Knowledge of DDR/LPDDR DRAM protocols and experience analyzing/debugging DDR interfaces and protocols Experience in the development of Memory Controller and PHY IPs Experience working with Memory IP, Error checking Code (ECC), and building scalable, efficient flows and processes Experience with designing state machines, data paths, arbitration and clock domain crossing (CDC) logic Exposure to Design For Test (DFT), understanding of scan and writing DFT friendly RTL Experience developing or integrating IPs with AMBA AXI, ACE-Lite, and CHI interfaces Familiarity with Unified Power Format (UPF) for simulation and synthesis Programming skills in C, PERL/Python An eye for detail and ability to work with multi-functional teams to identify challenges and requirements and translate those into IP development items Great communication and interpersonal skills ADDITIONAL REQUIREMENTS: Ability to work long hours and weekends as

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