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Principal Design Verification Engineer

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Austin, United States ARM Full time

Are you ready for a new and exciting challenge? If you are a self-motivated verification engineer with experience in PCIe and looking to make a difference in an innovative and inclusive team, you’ve come to the right place Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient, and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC. The collection of silicon proven interconnects, security IP, system controllers, debug and trace, and IP tooling are all designed, validated, and optimized to be used with Arm Cortex processors and Arm Mali Multimedia IP. Built upon the open AMBA interface standard, Arm System IP provides design teams with the foundation for building better systems. Job Overview:

The Arm CoreLink Coherent Mesh Network is designed for intelligent connected systems across a wide range of applications including networking infrastructure, storage, server, HPC, automotive, and industrial solutions. The highly scalable mesh is optimized for Arm processors and can be customized across a range of performance points. Responsibilities:

Our group is seeking dedicated verification engineers to deploy and implement next-generation PCIe designs and components. As a verification engineer in our interconnect team, you will work with our Austin-based team to implement tests, debug, and qualify future products in our roadmap. Required Skills & Experience:

Bachelors, Masters, or PhD in Electrical/Computer Engineering or Computer Science. 12+ years of experience in verification/RTL design. Proven capability and knowledge of PCI Express (PCIe) with a focus on the Transaction Layer, including memory types, ordering rules, and flows. Familiarity with the PCIe Data Link and Physical Layers. Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE, or AXI). Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches. Software engineering skills including understanding of object-oriented programming, data structures, and algorithms. Experience with functional coverage verification methods. “Nice To Have” Skills & Experience:

Experience in Formal Verification testbenches is a plus. Previous experience with high-speed bus protocols such as SATA, USB, and Ethernet. Knowledge of scripting languages such as Python or Perl. In Return:

At Arm, we are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape extraordinary. These behaviors are assessed as part of the recruitment process: Partner and customer focus. Collaboration and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. #LI-SA1

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