Microarchitecture & RTL Lead - I/O Engineering - Electrical (Semiconductor) Mountain View , Cal[...]

4 weeks ago


New York, United States NauWork Full time

**Location** Microarchitecture & RTL [Lead, I/O]

Engineering - Electrical (Semiconductor)

**Job Description** A NauWork client is seeking a Microarchitecture & RTL Lead - I/O to join its Mountain View, California team. If you are a talented, motivated engineer with experience designing and verifying megascale networking and computing devices, and are looking to grow in a fast-paced, dynamic startup environment this is a position to consider. They are looking for experienced logic designers who have the range to contribute across the full lifecycle of complex chip development, from system level requirements, to architecture and microarchitecture definition, through RTL implementation, verification, and tapeout. **Roles and Responsibilities:** *

Specify system-level and architecture requirements, and determine the overall strategy for achieving an optimal product, based on feedback from architecture and software teams, and key lighthouse customers. *

Microarchitecture development and specification. Work with system software, architecture, and modeling experts to analyze and specify the device-level functional and performance requirements for the high-speed IO interfaces. Define and invent any customizations or features that enable a highly differentiated solution. *

Perform detailed evaluation and selection of third-party digital and analog IPs for serdes, MAC/PCS, NOC, and PCIe/CXL endpoint controllers. Create development and integration plan for superset I/O block and interface functionality incorporating the IPs. *

Ownership of all aspects of the design process, from analysis of the design approach and tradeoffs, to specification, through RTL implementation. *

Functional verification support, from involvement in setting the verification strategy, to development of the test plan, through execution of the testing and coverage phases. *

Support for performance validation, to ensure that the high-speed IO interfaces enable the overall product to meet the strenuous system-level performance demands of modern data centers across diverse use cases. *

Delivery of a robust, high performance design that meets the timing, area, reliability, testability, and power requirements set by an aggressive cross-functional engineering team. *

Support silicon bringup and post-silicon testing, in conjunction with the software driver team. **Skills/Qualifications:** *

Proven industry experience and successful track record in microarchitecture and design of PCIe I/O blocks or similar memory-mapped host interfaces, preferably as part of network interface controller chips, smart-NICs, DPUs, I/O processors, or PCIe switches. *

Past technical lead responsibility for host-facing I/O block RTL design and/or verification, and/or evaluating third-party IPs such as PCIe endpoint controllers and Ethernet MAC/PCS. *

Thorough understanding of the following at the silicon implementation level: PCIe transparent & nontransparent bridging, CXL.mem, CXL.cache, RDMA, SR-IOV, PIPE interfaces, AXI buses, Network-on-Chip. *

Experience designing with NV-Link, Infinity Fabric, CCIX, QPI, or CXL. *

Expert current knowledge of high-performance digital logic design on advanced technology nodes. Track record of relentless design optimization to maximize performance, reduce latency, and achieve greater power/area efficiency within budgets. *

Minimum BSEE/CE + 15 years or MSEE/CE + 10 years experience. *

Proficient in SystemVerilog both as coder and reviewer. Python or other scripting language experience highly desired. **Questions:** *

Main: 833-NAU-WORK *

Email: *

Web: *

Jobs: *Category: Engineering - Electrical (Semiconductor)* *Position: Microarchitecture & RTL Lead - I/O* *Location: Mountain View, California* *Job Type: Direct-Hire, Full-Time*

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