Sr.-Principal ASIC Design Engineer

3 weeks ago


New York, United States Tripod Networking Full time

Location: San Jose, CA Will transfer H1's. Will consider relocation if needed.

Responsibilities: Micro-architecture specifications and participate in specification and test plan reviews. Architect and implement complex RTL designs. Integrate CPU and other relevant IPs into the CPU sub-system. Work with the physical design team to resolve implementation and timing issues and to optimize power. Required Qualifications: 6+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog. Experience in IP integration, specifically CPU IP into SoC. Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation Strong UVM exp. Familiarity with AMBA/APB/AXI Protocol Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C .... B.S. (M.S. preferred) degree in Electrical or Computer engineering.


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