FPGA Engineer
2 weeks ago
Description:
The scope of work consists of Design Verification of VHDL developed for an FPGA. The task will include DV planning (i.e., verification and coverage plan development), creation of test bench infrastructure whether from scratch or through re-use of existing code testcase development, testing, debug, and coverage closure. All DV code will be developed using best practices. Team leadership responsibilities may also be required for this role (schedule development/tracking, resource allocation, technical guidance, etc).
Tasks to include:
1. Coverage and Verification plan documents describing verification flows and constructs, functionality to be verified, and testbench usage
2. Work Breakdown Structure (WBS), Gantt charts and/or other forms of a plan showing task breakdown, duration estimates, hand-ins, milestones, and task assignments;
3. SV/UVM Testbench infrastructure environment, UVCs, monitors, predictors, checkers, coverage collectors required for verifying the VHDL implementing FPGA functionality.
4. SV/UVM testcases for configuring the testbench and for generating the stimulus needed to verify the VHDL implements the functionality described in the FPGA specification.
5. Associated scripts and flows necessary for verification and simulation
6. Issue tracking to ensure all issues uncovered are resolved satisfactorily.
7. Revision / release control of all design verification source code and documentation produced as described in items 3.1.1 thru 3.1.4, above
8. Code and functional coverage reporting
Skills:
Fpga, Asic, Verilog, Design verification, UVM, Systemverilog, Xilinx, Vhdl
Top Skills Details:
Fpga,Asic,Verilog,Design verification,UVM,Systemverilog
Additional Skills & Qualifications:
Active Secret Clearance
1. Required Design Tools and Revisions
2. All tools in sections items 2 and 3 (below) will be provided by BAE Systems.
3. Mentor tool set:
Qualifications:
1. SV/UVM Testbench infrastructure environment, UVCs, monitors, predictors, checkers and testcases needed for verifying the VHDL implementing FPGA functionality
2. Scripts, constraints, setup, or other associated files related to the testbench
3. Coverage and Verification plan documents describing verification flows and constructs, functionality to be verified, and testbench usage
4. Code and functional coverage reports
Experience Level:
Intermediate Level
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.
Diversity, Equity & Inclusion
At Actalent, diversity and inclusion are a bridge towards the equity and success of our people. DE&I are embedded into our culture through:
+ Hiring diverse talent
+ Maintaining an inclusive environment through persistent self-reflection
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+ Ensuring growth opportunities for our people
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com (%20actalentaccommodation@actalentservices.com) for other accommodation options.
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