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Senior Design Verification Engineer
1 month ago
Mountain View, United States eInfochips (An Arrow Company) Full timeJob Title: Senior Design Verification Engineer (eInfochips Inc.)Resource will work onsite from day one at 1045 La Avenida St. Mountain View, CA 94043 (5 days onsite)Experience range - 10-15 yearsWhat You'll Be Doing:Strong PCIe expertise along-with complex SoC debug is mustAt-least 10+ years of experience in System Verilog HVL and C/C++.At-least 10+ year of...
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Senior Design Verification Engineer
1 week ago
mountain view, United States eInfochips (An Arrow Company) Full timePosition: Senior Design Verification EngineerLocation: Mountainview, California What You’ll Be Doing:Strong PCIe expertise along-with complex SoC debug is must. At-least 10+ years of experience in System Verilog HVL and C/C++.At least 10+ year of experience in SV/UVM.Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to...
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Senior Design Verification Engineer
1 month ago
Mountain View, United States eInfochips (An Arrow Company) Full timePosition: Senior Design Verification EngineerLocation: Mountainview, California What You’ll Be Doing:Strong PCIe expertise along-with complex SoC debug is must. At-least 10+ years of experience in System Verilog HVL and C/C++.At least 10+ year of experience in SV/UVM.Porting/Testing in FPGA & Emulation (Zebu) Hardware realization Platform is good to...
Senior Design Verification Engineer
2 months ago
Job Description:
- Plan the verification of complex design IP/SoC like CPU/Core/GFX block.
- Develop tests using UVM.
- Identify and write functional coverage for stimulus and corner cases.
- Analyze and debug test failures with designers to deliver functionally correct design.
- Assembly tests for any ISA is strongly desired but not required.
- Close coverage to plug verification holes and meet tape out requirements.
- IP integration DV.
- Stimulus generation tools development and automation.
Qualifications:
- Experience in design verification with a proven track record of delivering complex CPU or GPU’s.
- CPU/GPU Functional Verification Experience is Required.
- Should be able to write the UVM Code and understand the design.
- In depth knowledge of verification principles, testbenches, stimulus generation and UVM based test environments.
- Solid understanding of computer architecture.
- Substantial background in debugging RTL (Verilog) designs.
- Good Knowledge of VCS Simulation and Scripting language such as Python.