Senior ASIC Physical Design PPA Engineer

4 weeks ago

Austin, United States NVIDIA Full time

We are now looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

What you'll be doing: Drive physical design and timing of high-frequency and low-power designs

Focus on improving the PPA (Performance, Power, Area) for the next generation NVIDIA designs by working with cross-functional teams

You will focus on generating new ideas, validating those, putting together flows/methodologies around those, and incorporating those in NVIDIA’s designs

Apply knowledge and gain experience in ASIC design including RTL and logic design, physical and circuits design, and timing and power convergence

What we need to see: BS (or equivalent experience) in Electrical or Computer Engineering with 8+ years experience or MS (or equivalent experience) with 6+ years experience in Physical Design

Expertise in physical synthesis and deep understanding of RTL/logic and equivalence checking to achieve better QOR (quality of results)

Good understanding of Place-and-Route design as well as associated tools/flows, ability to analyze physical DBs (databases) and drive new ideas

Hands-on experience in STA and timing closure including multi-mode analysis, timing constraints generation and management, and timing convergence

Expertise in identifying timing bottlenecks (in design and process) and craft solutions to address those

Explore and implement low power design ideas by finding the right balance with timing and area

Good understanding of process and technology nodes, process variations and signal integrity related issues and modeling, and make design recommendations to address those

Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and industry-standard EDA tools

Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies

Strong interpersonal and communication skills to work across different domains of ASIC design, collaborate and work with Arch, RTL, DFT, and physical design teams

Ways to stand out from the crowd: Background in high-performance and low-power designs

Understanding of Device physics, Knowledge of circuits, SPICE simulations, and/or transistor level STA.

Ability to develop new methodologies/flows as well as workflows to aid design convergence.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you. The base salary range is 164,000 USD - 304,750 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits.

NVIDIA accepts applications on an ongoing basis. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

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