Verification Engineer III
3 weeks ago
Job Title: Verification Engineer III
Duration: 12 mos. + potential extension(s) and/or conversion
Location: Denver, CO, New York, NY , Houston, TX , Los Angeles, CA , and San Diego, CA
Description:
Job Responsibilities:
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design, Firmware and Architecture teams
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Required Skills/Experience:
7+ years' experience working on IP/SS/SoC verification using UVM / SV based testbenches (must have)
3+ years developing HW/SW co-design based tests (writing C code to run on internal MCUs in parallel with SV TB) (must have)
3+ years GLS (Gate Level Simulations) experience (must have)
Enabling gate level simulations and power aware gate level simulations in a System Verilog testbench.
Extensive experience running GLS, GLS w/SDF, power aware GLS and debugging complex X-propagation and timing issues on interfaces
3+ years working on externally sourced VIPs (eMMC, UART, SPMI, I2C/I3C, etc) (nice to have)
Experience owning an IP end to end (testplan creation, TB and test development, coverage closure) (nice to have)
Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation, Power Aware
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Education/Experience:
Bachelor's degree in Electrical Engineering, Computer Science or equivalent experience.
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