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Senior Staff Engineer, Mixed Signal Modeling and Design
4 days ago
Job Description
Job Description
About InnoPhase, Inc.
INNOPHASE
is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications.
Are you looking to grow your career at a company that 93% of our current staff approve of our leadership, values, and goals?
To learn more about InnoPhase, check out InnoPhase's ceritification profile at
GreatPlacetoWork.com
and our website at
www.innophaseinc.com.
Senior Staff Engineer, Mixed Signal Modeling and Design:
You will be responsible for providing technical leadership in developing novel/game-changing cellular infrastructure radio solutions for connectivity and communications. You will be a key contributor to our solutions features, architectures, device functional specifications, and performance. This individual may also oversee a team of
modeling/verification
engineers and supporting other discipline teams to bring the SoC device to successful mass production.
This full-time California position is based in San Diego, San Jose, or Irvine.
Key Responsibilities
Technical leadership in developing models for RF and analog IPs
Technical leadership in driving mixed signal and/or SOC verification
Mentoring other modeling engineers
Hands-on contribution in all aspects of the modeling, verification, and flow developments
Design of analog and mixed signal IPs, including but not limited to ADCs, PLLs, OpAmps and bias circuitry
Develop and improve test automation scripts
Working closely with analog, digital, and Firmware design engineers
Presenting to peers and management
Job Requirements
MS in Electrical Engineering with coursework in analog and digital circuits or related field
15 or more years of hands-on experience in analog IP design, modeling and verification
Comprehensive knowledge of mixed-signal and digital behavioral modeling and verification flows
Good understanding of CMOS device operation and construction
Knowledge of verification languages like Verilog/ Verilog A, SystemVerilog, RNM, Verilog-AMS, System-C, etc.
Expert in IC design, IP functions, and topologies
Experienced in modeling and designing complex analog IPs such as PLLs, ADCs, SerDes, RF receivers, and transmitters
Highly effective at debugging simulation results
Hands on experience making precise analog, digital measurements using typical laboratory instruments and techniques
Able to own the overall test bench development working with the digital and firmware engineers
Analytical and disciplined problem solver
Team player with a strong sense of urgency to meet product needs on time
Good verbal and written communication and presentation skills
Desirable Skills
Ability to perform both circuit design and AMS modeling
Knowledge of standard verification flows including UVM, testbench automation, and coverage-based metrics
Experience in automation script development in Python
Experience as a team lead or manager
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San Diego, United States InnoPhase Full timeJob DescriptionJob DescriptionAbout InnoPhase, Inc.INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our...
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San Diego, United States InnoPhase Full timeJob DescriptionJob DescriptionAbout InnoPhase, Inc.INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our...
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