Contract Hardware Engineer Sr.
3 weeks ago
Location:- Mountain View, CA 94043
Duration:- 12 months
Pay rate:- $80/hr on W2 & $90/hr on C2C
Note:
This role is similar to RTL design Engineer with strong experience in high speed PCIe designs and protocols, digital design principles in SoC and/or IP development, must have design background in Arteris NoC (Network on Chip) RTL generation or based on any other NoC tool
What You'll Be Doing:
- 7+ years of related technical engineering experience
- 5+ years of experience applying digital design principles in SoC and/or IP development.
- Proficient in Verilog/System Verilog coding constructs.
- Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
- Experience with high speed PCIe designs and protocols.
- Experience with Industry standard interface protocols such as AXI, APB, etc.
- Experience with ARM Fabric IPs.
- Experience with IPXACT.
- Understanding of Computer Architecture fundamentals.
- Ability to write scripts using Python, Tcl, Perl etc.
- Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
- BS or MS in Electrical Engineering (or equivalent)
- MUST HAVE design background in Arteris NoC (Network on Chip) RTL generation or based on any other NoC tool.
- Proficiency with UPF (Low power intent)
- Proficiency in clock crossing techniques.
- Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. NoC tool
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