Principal PHY/MAC RTL Design Engineers

In this role you will be implementing MAC, PHY algorithms for industry best low power IoT connectivity devices. These devices deliver next generation connectivity technologies at lowest power consumption. You will work with highly motivated team members across various cross functional groups such as RF & baseband systems, and firmware. Roles &...

Wireless MAC ASIC Design Engineer (All levels) As a member of our engineering team, you will work on the latest WLAN technology and product development. Successful candidates will be participating in the design of leading edge ASICs for Wireless Connectivity SoC platform. Responsibilities The Wireless MAC ASIC design engineer is responsible for the design...

Job Description: ASIC Design & RTL Skills Architecture exploration and improvements Micro-architecture development includes interface definition, state machine, data & control path definition, design partitioning. RTL development using Verilog, System Verilog Lint, CDC, Synthesis, & Power Optimization Soft and hard IP integration Collaboration with...

Job Description: ASIC Design & RTL SkillsArchitecture exploration and improvementsMicro-architecture development includes interface definition, state machine, data & control path definition, design partitioning.RTL development using Verilog, System VerilogLint, CDC, Synthesis, & Power OptimizationSoft and hard IP integrationCollaboration with verification...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...

Job Description: Join Innophase IoT group as a hands-on PHY Verification Engineer/Lead and be responsible for Low-power WiFi, BT/BLE verification. You will be involved in the design development cycle, which includes participating in high-level product specifications, UVM Testbench design, test planning, working closely with Systems, SW, and design engineers....

Design and simulate state-of-the-art physical layer Wireless Communication System algorithms for very high data rate applications. Implement fixed-point models and perform detailed performance investigation to allow performance sign-off and enable RTL bit-exact development. Work with digital designers to realize these algorithms with power and area efficient...

OPENEDGES develops AI edge computing semiconductor IPs, so that more people can enjoy AI technology closer. Location: San Jose, CA, USA or Austin, TX, USA Position: Principal Design Engineer OPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs...

OPENEDGES develops AI edge computing semiconductor IPs, so that more people can enjoy AI technology closer. Location: San Jose, CA, USA or Austin, TX, USA Position: Principal Design Engineer OPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs...

Staff/Sr. Staff PHY Design Engineer Job Description: Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT/BLE micro-architecture and design. You will be involved in the design development cycle, which includes participating in high-level product specifications, RTL development, working closely with Algorithm and...

OPENEDGES develops AI edge computing semiconductor IPs, so that more people can enjoy AI technology closer. Location: San Jose, CA, USA or Austin, TX, USA Position: Principal Design EngineerOPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs...

OPENEDGES develops AI edge computing semiconductor IPs, so that more people can enjoy AI technology closer.📍 Location: San Jose, CA, USA or Austin, TX, USA📍 Position: Principal Design EngineerOPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip...

OPENEDGES develops AI edge computing semiconductor IPs, so that more people can enjoy AI technology closer.📍 Location: San Jose, CA, USA or Austin, TX, USA📍 Position: Principal Design EngineerOPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip...

About InnoPhase IoT If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you'll find...

About InnoPhase IoT If you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of worknot just singing the same song every day, you'll find...

OPENEDGES develops AI edge computing semiconductor IPs, so that more people can enjoy AI technology closer. Location: San Jose, CA, USA or Austin, TX, USA Position: Principal Design Engineer OPENEDGES is the world's only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Hands-on work with Cadence customers in the areas of Frontend Digital Design Implementation including Synthesis, DFT and Logical Equivalence, Low Power, Power Characterization. Lead technical campaigns and strategies...

Must have more than 10+ years of work experience as RTL Design Engineer Job Description:- Need strong RTL engineer with solid expertise in CDC/RDC. its an immediate opportunity. 1 expert in CDC/RDC (using Synopsys Spyglass tools) Ability to debug CDC/RDC issues and have experience working with both front end and backend designers in resolving such...

RTL Design Engineer - Senior (US)Location: Onsite San Jose, CA6-12 months contract JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design....

Must have more than 10+ years of work experience as RTL Design EngineerJob Description:-Need strong RTL engineer with solid expertise in CDC/RDC. its an immediate opportunity. 1 expert in CDC/RDC (using Synopsys Spyglass tools)Ability to debug CDC/RDC issues and have experience working with both front end and backend designers in resolving such...