SoC Integration Engineer

2 weeks ago

San Jose, United States Hire IT People Full time

The Work: The ideal candidate can help along the design flow to establish synthesis runs with the related timing constraints, perform Lint,

CDC, DFT checks, support

regression and release process and analyze STA timing results.

Here’s what you need:

A minimum of 3 years of experience with STA (Static Timing Analysis) and PrimeTime and related timing constraints methodology and SDC constraints language A minimum of 3 years of experience RTL Integration, 3rd Party IP RTL through Lint, CDC check, DFT check with spyglass or VC static and generate clean reports Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience) Background in subsystem integration There is a need to have proper representation for NEEV There is some customization so having RTL background would be good Basic Python knowledge with good understanding of digital design Background in AMBA Protocol such as, AXI, APB, AHB, QCH, Expected to deliver basic design collateral : Lint, CDC, RDC, UPF Basic understanding of CoreConsultant Half the team exposed to UVM and basic to good UVM working/debug background knowledge

Bonus points if: Proficient with System Verilog/Verilog RTL source code Proficient with Synopsys Design Compiler and/or Design Compiler Ultra Python, tcl and other typical scripting languages Debug flow and tool errors Familiar with vaml Familiar with setting up and debugging GLS runs Familiar with bug tracking systems like Jira Familiar with revision control systems like Git

Nice to have: Low power design background for front-end Background in high speed IOs and Protocol such as MIPI, PCIE, DDR, Serdes Basic understanding of MMU-600, SST, VFC and SEQ [custom DMA] Qualifications: Bachelor’s Degree or equivalent (12 years) work experience (Associate’s Degree with 6 years of experience). Minimum 3 years of experience with STA and PrimeTime, including timing constraints methodology. Background in AMBA Protocol (AXI, APB, AHB, QCH). Experience with RTL integration, linting, CDC checks, and DFT checks. Basic understanding of CoreConsultant and AMBA protocols. Desired Skills: Proficiency with System Verilog/Verilog RTL source code. Experience with Synopsys Design Compiler. Familiarity with Python, Tcl, and other scripting languages. Exposure to UVM and bug tracking systems like Jira. Basic understanding of low-power design and high-speed IO protocols (MIPI, PCIe, DDR, Serdes).

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