Senior Physical Design Engineer
4 weeks ago
STA Lead
Physical Design activities for MCU/MPU SoC's.
• Expertise in developing, implementing and verifying STA constraints
• Expertise in efficient closure of Subsystem as well as SoC-level timing including running optimization on PTECO for timing and Power
• Knowledge of industry standards and practices in Timing closure, Physical Design, Floor-planning, and Place & Route
• Knowledge of basic Architecture and Verilog to collaborate with RTL and IP design teams for timing fixes
• Contribute to timing flow and methodology improvements
Key Challenges:
• Demonstrate a strong knowledge of all aspects of timing and synthesis for a wide variety of designs.
• Understand crosstalk, noise, OCV, timing margins. Familiarity with Clock specs, jitter, IR drop, spice analysis.
• Working with multi-site teams for execution
Cross functional aspects:
• Work with methodology teams to constantly improve flows and processes
Job Qualifications:
• BS/MS in Electrical or Computer Engineering
• 5-10+ years of experience in Static Timing Analysis
Experience with STA Lead roles
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