Senior Verification Manager_

1 week ago

Santa Clara, United States NVIDIA Full time

We are now looking for a Senior Emulation Manager For more than two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics. With a rare focus on this field, we offer specialized platforms for the gaming, professional visualization, data center, and automotive markets. Our work is at the center of the most consequential mega-trends in technology — virtual reality, artificial intelligence, and self-driving cars. Join NVIDIA's elite emulation team in Santa Clara. Our focused team takes GPUs/SoCs designs and program the emulators to behave like our GPUs/SOCs. Our emulators are connected to real PCs running the operating system and the designs used to exercise the emulated design. Are you ready to tackle exciting problems and craft solutions? Come check out our team What you will be doing: + You will design, implement, and verify Emulation/FPGA prototypes of the industry's leading GPUs and SOC's. This position requires a wide range of skills, and extraordinary problem solving ability. + This is a role for a versatile engineer that includes RTL design, verification, Emulation/FPGA partitioning and implementation, and lab based bringup of the SoC/GPU chips. + Lead and manage a team of Emulation/FPGA Engineers. + Collaborate with architects, designers, software engineers, and verification teams to accomplish your tasks. + Develop and operate tests on state of the art emulators and in post-silicon validation and assist in bring-up processes from prototyping through post-silicon validation. + You'll build standalone test cases for tool issues encountered in the emulation compile and runtime flows + Manage emulation of various of chips like GPUs, SOC, CPU, NIC + Architect emulation methodologies to verify designs and to get SW developed on emulation and FPGA platforms + Track emulation testplans of various chips and make sure the testplans hit 100% pass rate within the chip deadlines What we need to see: + B.S. or M.S. EE/CS/CE (or equivalent experience) with 12 + years working in the semiconductor industry or equivalent experience + 5+ years of leading a team + Extensive design verification experience (RTL, Emulation, or Prototyping) + Having a strong proficiency in emulator hardware knowledge is key for success in this fast-paced environment. + Ability to architect, implement and verify modules for FPGA interconnect. + You are familiar with both Linux and Windows environments and are proficient in Verilog, Perl, and Make + Hands on Emulation/FPGA debug methodologies. Both simulation based verification and debug skills necessary. + Shown experience with a source control system, such as Perforce. + Hands on experience with lab debug equipment, such as oscilloscopes and logic analyzers. NVIDIA is on the move and our technology and vision position us as one of the world’s most desirable employers. We have some of the most forward-thinking and talented people on our journey. If you're inventive and autonomous, we want to hear from you The base salary range is 232,000 USD - 356,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits (vidia.com/en-us/benefits/) . NVIDIA accepts applications on an ongoing basis. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. NVIDIA is a Learning Machine NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and the metaverse is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA .

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