SoC Power Modeling Engineer – Optimize AI/ML
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Apple Inc. in Cupertino is seeking an ASIC power modeling engineer to design and validate power delivery and DVFM points for IPs and SOCs. You will model and optimize power behavior across multiple Apple silicon blocks to support energy-efficient products.
You will collaborate with architecture, design, thermals, PMIC and lab teams to correlate models with hardware data, enabling accurate power predictions and robust silicon performance.
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