US_East | Software Developer

DFT Engineer

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential Submit candidates under their legal name and use only Capgemini template

Role: DFT Engineer

Work Location: Santa Clara, CA

Rate: $85.00/hr

Qualification/Experience/Skills Required:

• Ability to define and describe (write specification for) system architecture, external interfaces, register definitions and operations, major partitions
• Ability to write clear, concise documents and diagrams (timing, state machines, register maps, memory organization, synchronization sequences, etc.) to describe functional and operational (parametric) aspects of a complex SoC
• Domain knowledge of various software applications and their underlying hardware requirements (e.g., networking, AI, Machine Learning, storage devices, IoT)
• Experience in Digital module design and micro-architecture
• Experienced at modeling complex state machines, data-paths and bus protocols/high speed (bandwidth) interfaces such as PCIe
• 3+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST
• Experience with Synopsys DFT Complier, Tetramax and VCS is required
• Experience with TestKompress, Tessent and Modus/Encounter tool suite is a plus
• Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics
• Hands-on expertise in writing System Verilog and VHDL
• Hands-on in Perl/Tcl/Unix scripting
• Excellent analytical, and problem-solving skills
• 8+ years' industry experience, Master's degree or equivalent in EE or Computer Engineering (CE)

Roles & Responsibilities:

• Write clear, concise specification for an SoC including functional and timing descriptions for top level pins/ports/interfaces, registers and memories, state machines, datapaths, operating modes, exception/error handling, clocking, reset, power domains, etc.
• Describe parametric/operating environment requirements including performance, power, area (PPA) targets, temperature and process ranges, IO pads, parametric tests, etc.
• Interact with other system architects to define the application environment for the SoC being designed (firmware and OS requirements, external storage devices, sensor/analog components, etc.)
• Provide SoC (top) level constraints and partitions for RTL/Logic designers, floorplan & PD engineers, DFT requirements
• Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation
• Verify DFT circuitry and interface with other blocks, debug timing simulation issues
• Closely work with physical design team to generate and validate timing constraints
• Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning
• Be able to work independently and own the complete task from DFT specification to final pattern delivery for sub-system and/or SOC
• Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage
• Technical interaction with engineering team

Education: BSEE, in Electrical/Computer OR MSEE, in (Electrical/Computer)