Staff Design Verification Engineer

About SiFiveAs the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
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Job Description

About the Role
SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core units. This is a Staff individual-contributor role within the CPU Design Verification organization, aligned to high-performance core development.
This role spans key core areas such as Frontend, Midcore, Load-Store Unit, and Hardware Prefetch, and is aimed at engineers who can go beyond executing assigned tests to define strategy, identify verification gaps early, solve difficult microarchitectural problems, and raise the quality bar for the broader team.
You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, risks are identified early, and signoff quality is achieved with strong technical judgment and scalable methodology.
ResponsibilitiesOwn verification planning and execution for one or more high-performance out-of-order CPU core areas, with typical scope across Frontend, Midcore, Load-Store Unit, Hardware Prefetch, or related core-level interactions.
Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural behavior.
Define verification strategies for challenging behaviors such as instruction fetch, branch prediction, issue and dispatch behavior, pipeline interactions, load/store ordering, hazard handling, memory consistency, and hardware prefetch correctness.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.
Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification quality.
Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
Contribute reusable methodology, infrastructure, and technical guidance that improves productivity and verification quality across future core generations.
Minimum QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
Strong hands-on experience with SystemVerilog and UVM-based verification.
Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
Experience in one or more high-performance CPU areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
Strong knowledge of verification flow methodology, including test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.
Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
Preferred QualificationsExperience with out-of-order core verification.
Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
Experience collaborating with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area.
Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.
What Success Looks LikeVerification plans capture the real architectural and microarchitectural risks early and completely.
Difficult CPU bug