FPGA Design Verification Engineer

Join to apply for the FPGA Design Verification Engineer role at UST. 4 days ago Be among the first 25 applicants. Who We Are Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world. Role Description FPGA Design Verification Engineer, Technical Lead II – VLSI. UST is a mission-driven group of 29,000+ practical problem solvers and creative thinkers in more than 30 countries. Our entrepreneurial teams are empowered to innovate, act nimbly, and create a lasting and sustainable impact for our clients, their customers, and the communities in which we live. With us, you’ll create a boundless impact that transforms your career—and the lives of people across the world. We’re seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team, working on state-of-the-art technologies. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products. The Opportunity Create and maintain test benches using industry‑standard verification methodologies (e.g., UVM, SystemVerilog, RTL). Write and debug test cases to verify functionality, performance, and corner cases. Identify and debug issues, working closely with design engineers to resolve them. Participate in design reviews and contribute to the overall verification strategy. Stay up‑to‑date with the latest verification methodologies and tools. This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required. What You Need Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of experience in FPGA design or verification. Familiarity with hardware description languages (e.g., VHDL, Verilog). Strong understanding of FPGA, ASIC, RTL design principles and architectures. Proficiency in SystemVerilog and UVM verification methodology. Experience with Linux operating system. Experience with industry‑standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps). Experience with high‑speed I/O design and protocols. Knowledge of PCIe, I2C, SPI, etc. Hands‑on experience with lab debugging tools including logic analyzer, oscilloscope, and JTAG. Excellent debugging and problem‑solving skills. Desired Skills: Experience in hardware validation or embedded test automation. Experience with scripting languages (e.g., Python, Perl). Compensation & Benefits Role Location: Remote Compensation Range: $101,000–$152,000 Full‑time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro‑rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company‑paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short‑ and long‑term disability benefits. Regular employees may purchase additional voluntary short‑term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico. Part‑time employees receive 6 days of paid sick leave each year (pro‑rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. Full‑time temporary employees receive 6 days of paid sick leave each year (pro‑rated for new hires throughout the year) and are eligible to participate in the Company’s 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance. Part‑time temporary employees receive 6 days of paid sick leave each year (pro‑rated for new hires throughout the year). All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws. Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, status as a protected veteran, or any other applicable characteristics protected by law. We will consider qualified applicants with arrest or conviction records in accordance with state and local laws and “fair chance” ordinances. UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance. Seniority Level Mid‑Senior level Employment Type Full‑time Job Function Engineering and Information Technology Industries IT Services and IT Consulting Skills FPGA, RTL, SystemVerilog #J-18808-Ljbffr