Principal IO Design Architect, HBM

Position OverviewWe are searching for a Principal HBM IO Architecture Design engineer own the development of the PHY IO on the interface die in HBM. This position you will be responsible for the development including defining design target, developing spec, architecting IO / clocking / datapath, being responsible for design optimization and verification. Use of both analog and digital CMOS design skills will be needed to work on the various circuits you would be responsible for. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful.ResponsibilitiesIO and datapath design architect for HBM productsDesign low-power high-speed Tx/Rx clock treeAnalyze timing jitter and variation to improve speed and optimize designContribute to cross‑group communication to work towards standardization and group successProactively solicit guidance from Standards, CAD modeling and verification groups to ensure design qualityDrive innovation into the future Memory generation with a multifaceted work environmentQualificationsPrior industrial experience in high‑speed clocking design at 16 Gbps speedGood IO circuit design background with familiarity of both analog and digital design; simulation experience requiredSolid knowledge of IO design principles for practical design tradeoffs on speed / area / power / complexityExperience with circuit verification and optimization including layout verification and parasitic extractionsFamiliar with one or more off‑chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc.Good understanding of FinFET device characteristics and hands‑on design experienceExcellent problem‑solving and analytical skillsStrong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers verbally and in writingUnderstanding of device physics and basic CMOS processing techniques preferredPrior circuit debug experience through Product Engineering or equivalent preferredDesign‑to‑Design (D2D) design experience is a plusFamiliar with IP‑level verification and strong RTL debugging capabilities is a plusRequired ExperienceMinimum 5 years of proven experience in the Memory industry with an MS EE degree or 7 years with a BS EE or equivalent experience.BenefitsMicron provides a choice of medical, dental and vision plans in all locations, along with benefit programs that help protect your income if you are unable to work due to illness or injury and paid family leave. Additionally, Micron offers a robust paid time‑off program and paid holidays.EEO StatementMicron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship, status of disability, protected veteran status, gender identity or any other factor protected by applicable federal, state or local laws.Legal StatementsMicron Prohibits the use of child labor and complies with all applicable laws, rules, regulations and other international and industry labor standards.Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.AI alert: Candidates are encouraged to use AI tools to enhance their resume and application materials. However all information provided must be accurate and reflect the candidate’s true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website and the About Micron Technology Inc. page. #J-18808-Ljbffr