Sr. Principal DSP Architect

3 days ago


San Jose, United States Astera Labs Full time

OverviewAstera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. Discover more at www.asteralabs.com.Job DescriptionSenior Principal DSP Architect — you will join a team of DSP/Systems experts, digital designers, and mixed-signal design engineers developing advanced DSP SerDes for next generation 400G per lane wireline and optical interconnect for AI systems. The DSP architecture team is responsible for the following functions.Research novel modulation, equalization, and FEC techniques for 400G per lane wireline and optical systems.Create DSP and FEC algorithms, bit/cycle accurate C/C++ models, and hardware block specifications appropriate for RTL implementation.Collaborate with digital and firmware teams to optimize and implement DSP algorithms in hardware/firmware.Hands-on involvement in post-silicon performance tuning and optimization.Provide guidance on test plans for lab characterization.Provide support for internal customers deploying SerDes IP.Basic QualificationsMaster’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience with DSP architectures and algorithm development.Required SkillsSolid understanding of and experience with designing adaptive DSP algorithms.Solid understanding of the practical aspects of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation.Good programming skills in C/C++, Matlab or Python.Experience in guiding and testing the transfer of high-speed numerical algorithms from C/C++ to Verilog.Additional Useful SkillsFamiliarity with high-speed optical and electrical channels and the DSP algorithms for compensating their impairments.Reading knowledge of Verilog RTL and the ability to assist with the assessment of Verilog implementations of DSP algorithms.Experienced with modern version control and software management systems.Experience with error correction (Reed-Solomon, BCH, soft decoding) in high-throughput, low-latency systems.CompensationThe base salary range is $160,000.00 USD – $260,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.Apply for this jobTo apply, please follow the instructions on the company website. #J-18808-Ljbffr



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