Talent Groups | Design Verification Engineer | dallas, tx
7 days ago
Role: Design Verification Engineer
Location: Dallas, TX - Onsite
Contract
Job Description:
•The candidate will be responsible for writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for SoCs/Subsystems
•Create System Verilog / UVM verification environment.
•Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.
•Run regressions, debug test failures and file bug report as needed.
•Provide verification report as needed to show all implemented tests passing on the RTL.
Required Skills / Experience
•Candidate must have minimum 5 years of experience in functional verification
•Candidate must have strong knowledge of System Verilog and in UVM methodology
•Candidate must have knowledge of AXI, AHB protocol
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dallas, United States Talent Groups Full timeRole: Design Verification EngineerLocation: Dallas, TX - OnsiteContract Job Description:•The candidate will be responsible for writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for SoCs/Subsystems •Create System Verilog / UVM verification environment....
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