Senior FPGA Design Engineer

2 weeks ago


san diego, United States ManpowerGroup Full time

JD for the Senior FPGA RTL Engineer– 5-12yrs ONLY, no senior profiles

1) Expertise in FPGA design

2) Expertise in RTL design and FPGA integration using Verilog/System Verilog

3) Good Knowledge of synthesis , Place and Route and STA

4) Good understanding of bus protocols (AXI, AHB, ATB, APB)

5) Knowledge in constraints

6) Knowledge in FPGA pinning, schematic Review

7) Knowledge in debugging using inbuilt logic analyzers

8) Knowledge of one or more of the interface protocols

a. PCIe

b. DDR

c. Ethernet

d. I2C, UART, SPI

9) Expertise in setting up and using tools like

a. Xilinx/AMD FPGA tools

b. Xcellium

10) Understanding of scripting languages like Make flow, Perl ,shell, python etc

11) Board validation of FPGA platforms



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