ACL Digital | Design Verification Engineer | san jose, ca

Position: Design Verification EngineerLocation: San Jose/Austin (Onsite/Hybrid)Position Overview:5+ years of relevant experience in Design Verification.Experience with System Verilog and UVM is a must.Strong experience in testbench development such as UVM methodology.Experience in verification of SerDes IP block interfaces in a complex SoC fabric...

Role : Design Verification EngineerLocation : San Jose CA (Onsite)Responsibilities:● Develop verification methodology and testbenches for digital and mixed-signal blocks● Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnectsBasic Qualifications:● BS, MS in Electrical Engineering, Computer Engineering,...

Position: Design Verification EngineerLocation: San Jose/Austin (Onsite/Hybrid)Position Overview:5+ years of relevant experience in Design Verification.Experience with System Verilog and UVM is a must.Strong experience in testbench development such as UVM methodology.Knowledge of GPU, experience with Shader, Texture, or Memory System a...

Position: Design Verification EngineerLocation: San Jose/Austin (Onsite/Hybrid)Position Overview:5+ years of relevant experience in Design Verification.Experience with System Verilog and UVM is a must.Strong experience in testbench development such as UVM methodology.Knowledge of GPU, experience with Shader, Texture, or Memory System a...

Position: Design Verification EngineerLocation: San Jose/Austin (Onsite/Hybrid)Position Overview:5+ years of relevant experience in Design Verification.Experience with System Verilog and UVM is a must.Strong experience in testbench development such as UVM methodology.Knowledge of GPU, experience with Shader, Texture, or Memory System a...

Job Title: Senior Design Verification EngineerLocation : San Jose, CA or San Diego, CA (Hybrid)Contract RoleRequirement:BS/MS/PhD (or equivalent experience) 12+ years of relevant experience in Verification. Must have knowledge of entire testbench , flow, setup and Assigning taskVerification: Experience at all level - Block level - subsystem level.Proficient...

Job Title: Senior Design Verification EngineerLocation : San Jose, CA or San Diego, CA (Hybrid)Contract RoleRequirement:BS/MS/PhD (or equivalent experience) 12+ years of relevant experience in Verification. Must have knowledge of entire testbench , flow, setup and Assigning taskVerification: Experience at all level - Block level - subsystem level.Proficient...

Job Title: Senior Design Verification EngineerLocation : San Jose, CA or San Diego, CA (Hybrid)Contract RoleRequirement:BS/MS/PhD (or equivalent experience) 12+ years of relevant experience in Verification. Must have knowledge of entire testbench , flow, setup and Assigning taskVerification: Experience at all level - Block level - subsystem level.Proficient...

Role : Design Verification EngineerLocation : San Jose CA (Onsite)Responsibilities:● Develop verification methodology and testbenches for digital and mixed-signal blocks● Test plan, coverage analysis and closure for parallel link and SerDes IP blocks and on-chip interconnectsBasic Qualifications:● BS, MS in Electrical Engineering, Computer Engineering,...

Job Title: DFT Engineer Location: San Jose, CA (Hybrid)Duration: Contract Project Job Description: Responsibilities:● Develop and optimize DFT features for use in complex digital systems● Perform structural scan and at-speed scan insertion, automatic pattern generation, and scancoverage analysis (Cadence Genus w/ Modus or Siemens Tessent)● Create DFT...

Job Title: DFT Engineer Location: San Jose, CA (Hybrid)Duration: Contract Project Job Description: Responsibilities:● Develop and optimize DFT features for use in complex digital systems● Perform structural scan and at-speed scan insertion, automatic pattern generation, and scancoverage analysis (Cadence Genus w/ Modus or Siemens Tessent)● Create DFT...

Job Title: DFT Engineer Location: San Jose, CA (Hybrid)Duration: Contract Project Job Description: Responsibilities:● Develop and optimize DFT features for use in complex digital systems● Perform structural scan and at-speed scan insertion, automatic pattern generation, and scancoverage analysis (Cadence Genus w/ Modus or Siemens Tessent)● Create DFT...

Job Title: Senior Design Verification SpecialistLocation: San Jose, CA or San Diego, CA (Hybrid)Contract RoleRequirements:BS/MS/PhD (or equivalent experience)12+ years of relevant experience in VerificationMust have knowledge of entire testbench, flow, setup, and assigning tasksVerification: Experience at all levels - Block level - subsystem levelProficient...

Job title: Senior Physical Design Architect Location: San Jose, CADuration: Full Time (Permanent)Job Description:Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.Collaborate across teams (physical design, logic design, package, DFT and test).Hands-on synthesis and PnR using industry...

Job title: Senior Physical Design Architect Location: San Jose, CADuration: Full Time (Permanent)Job Description:Work closely with logic design team to define physical architecture and drive physical aspects during the design cycle.Collaborate across teams (physical design, logic design, package, DFT and test).Hands-on synthesis and PnR using industry...

***Candidate must sit onsite in San Jose, CA******Candidate must be able to work W2 perm position***Top SkillsMust have very strong system Verilog experience and some computer architecture experienceWants someone who hasn't worked from spec their whole career as wellLow-energy experience: clock gating, different ways to minimize circuit energy - come...

***Candidate must sit onsite in San Jose, CA******Candidate must be able to work W2 perm position***Top SkillsMust have very strong system Verilog experience and some computer architecture experienceWants someone who hasn't worked from spec their whole career as wellLow-energy experience: clock gating, different ways to minimize circuit energy - come...

***Candidate must sit onsite in San Jose, CA******Candidate must be able to work W2 perm position***Top SkillsMust have very strong system Verilog experience and some computer architecture experienceWants someone who hasn't worked from spec their whole career as wellLow-energy experience: clock gating, different ways to minimize circuit energy - come...

Job Title: Verification Engineer - FPGA Design ExpertAbout the Role:We are seeking an experienced Verification Engineer with a strong background in FPGA design to join our team in San Jose. The ideal candidate will have a deep understanding of Verilog, UVM, and digital design, with experience in lab skills and debugging.Key Responsibilities:Develop and...

Job Description:As a Staff Analog IC Design Engineer, you’ll be responsible for analog and digital circuit design, simulation, layout supervision and verification, preparation of test plan for the test group, product characterization, bench to test correlation, bench evaluation both at the silicon level and at the applications level, and documentation....